1. Field of the Invention
The present invention relates to a semiconductor device, specifically to an integrated circuit employing a Schottky gate field effect transistor (metal-semiconductor field effect transistor MESFET). More specifically, it relates to a circuit construction of a logic gate composed of MESFETs using compound semiconductors.
2. Description of the Prior Art
An integrated circuit employing silicon (Si) as a semiconductor material is inferior to an integrated circuit employing a compound semiconductor such as GaAs as a semiconductor material, with regard to the speed of operation the power consumption, etc. A compound semiconductor integrated circuit formed of GaAs or the like has superior characteristics such as an increased speed of operation a reduced power consumption. Therefore, utilization of the integrated circuit employing a compound semiconductor to a digital application field is strongly desired. A compound semiconductor integrated circuit, such as a GaAs integrated circuit, is composed of Schottky-gate field-effect transistors (MESFETs) and hence differs from an Si integrated circuit.
Various circuits employing MESFETs have become known for forming a logic gate which is an extremely important circuit component in digital integrated circuits.
FIG. 1 shows a structure of a DCFL (direct-coupled FET logic) circuit which is one example of a typical conventional logic gate employing MESFETs.
Referring to FIG. 1, the DCFL circuit comprises a normally-off type MESFET 1 with its gate receiving an input signal, its source being connected to the ground, and its drain providing an output signal. A load 2 is connected between the drain of the MESFET 1 and a power supply V.sub.DD. The load 2 may be a resistor or a MESFET.
The DCFL circuit has a small power consumption and therefore it is suitable for a very large scale integrated circuit (VLSI). However, the DCFL circuit has a disadvantage in that it has a small logical swing. More specifically the logical swing of the DCFL circuit output is usually about 500 mV, since the logical high level thereof is clamped by the forward threshold voltage of the Schottky gate and the logical low level thereof is at a potential slightly higher than the ground level (normally 0.2 V). Consequently, the noise margin and the margin for any threshold voltage variation of the MESFET are not large enough in the DCFL circuit.
In addition, the low level output potential needs to be sufficiently low in the DCFL circuit, so that a resistor having a large resistance value or a MESFET which passes a sufficiently small current, must be used as the load 2. If the circuit output is taken off between the load 2 and the drain of the MESFET 1 as shown in FIG. 1, the current drivability of the output is small since the load 2 has an effectively large resistance value. Specifically, if the DCFL circuit is used as a current source, the drivability of this current source is extremely small.
As described above, the DCFL circuit is not suitable for a circuit comprising a long wiring and/or a large number of fan-outs or branches.
FIG. 2 shows a structure of a BFL (Buffered FET Logic) circuit which is another example of a conventional logic gate employing MESFETs.
Referring to FIG. 2, the BFL circuit comprises a combination of a switching stage performing a switching operation in response to an input signal, and a buffer stage for a current amplification and for a level shift of the switching stage output (i.e. the drain output of the MESFET 4).
The switching stage comprises a normally-on type MESFET 4 with its gate receiving an input signal, its source connected to ground potential and its drain connected to a power supply V.sub.DD through the load 3 and to the gate of the MESFET 5. The load 3 maybe a resistor or a MESFET.
The buffer stage comprises a normally-on type MESFET 5 having its drain connected to the power supply V.sub.DD, its gate is connected to the drain of the MESFET 4, and its source is connected to the anode of a Schottky barrier diode 6. The Schottky barrier diode 6 shifts the level of an output signal and has its anode connected to the source of the MESFET 5, its cathode connected to the drain of the MESFET 7, an output terminal and a normally-on type MESFET 7 having its drain connected to the cathode of the diode 6 and its gate and source both connected to a potential V.sub.CS.
In the BFL circuit, a MESFET having a threshold voltage of -0.5 V to -2.0 V is commonly used, whereby the logical swing of the output becomes as large as about 1.5 V. Since the BFL circuit has a large logical swing, it provides enough margin for the variation of the threshold voltage. The noise margin thereof is also large.
In addition, in the BFL circuit, the normally-on type MESFET which has larger current drivability compared with the normally-off type MESFET, is used. Furthermore, the BFL circuit has a buffered amplifying stage. Accordingly, the current drivability of the BFL circuit output is larger than that of the DCFL circuit. The BFL circuit has superior characteristics in the logical swing in the current drivability, etc. However, the power consumption of the BFL circuit is as large as 1 mW to several mW per gate. Therefore, the BFL circuit is not suited as a circuit structure forming a large scale integrated circuit.
Further, power is constantly consumed in the buffered amplification stage in the BFL circuit. Therefore, it is not an effective circuit in terms of the gate power consumption with respect to the current drivability at the time of gate switching.
In addition, the BFL circuit comprises at least one diode for a level shift. Therefore, it is difficult to reduce the logical swing of the output to a value smaller than 1.5 V.
Generally, the variation of the threshold voltage in a wafer surface has been a problem in fabricating a MESFET IC on a GaAs substrate. The GaAs ICs cannot be fabricated with a high yield unless the threshold voltages in the wafer surface are uniformly distributed. The conventional fabrication technique results in MESFETs having a substantial variation of threshold voltages, fabrication technique, so that a difficult technical problem arises in the application of the DCFL circuit having a small logical swing as described with reference to FIG. 1, to the GaAs IC. It appears that the threshold voltage of the DCFL circuit is somehow related to dislocations in the wafer or to other crystalline defects. However, a direct relationship has not yet been established. Recently, it has become possible to keep variations of the threshold voltage to less than several 10 mV in an IC comprising MESFETs fabricated on a GaAs wafer. The reason for these relatively low variations appears to be that it has become possible to fabricate GaAs single crystals with with a sufficiently high uniformity. If the variations of the threshold voltage are several 10 mV, a logical swing as large as 1.5 V in the BFL circuit means that the margin for the threshold voltage is too large. Therefore, a power consumption as small as possible is more desirable than the large output logical swing of 1.5 V of the BFL circuit. In other words, the large power consumption of the BFL circuit has become a big problem.